Publications

Journals

  • “Efficient DVFS for Low Power HEVC Software Decoder”
    Erwan Nogues, Julien Heulot, Glenn Herrou, Ladislas Robin, Maxime Pelcat, Daniel Menard, Erwan Raffin, Wassim Hamidouche
    Journal of Real-Time Image Processing (JRTIP), 2016
    Link to the article
  • “Low power HEVC software decoder for mobile devices”
    Erwan Raffin, Erwan Nogues, Wassim Hamidouche, Seppo Tomperi, Maxime Pelcat, Daniel Menard
    Journal of Real-Time Image Processing (JRTIP), 2015
    Link to the article
  • “Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture” – improved and extended version
    Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floc’h, Krzysztof Kuchcinski, Stéphane Chevobbe and Stéphane Guyetant
    International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2012
    Link to the article
  • “Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel”
    Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin
    ACM Transactions on Design Automation of Electronic Systems (TODAES), 2009
    Link to the article

Conferences

  • “Scalable HEVC Decoder for Mobile Devices: Trade-off between Energy Consumption and Quality”
    Erwan Raffin, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat, Daniel Menard
    Conference on Design and Architectures for Signal and Image Processing (DASIP 2016), Rennes, France, 2016
    Best Paper Award – Web links: DASIP2016
  • “A DVFS based HEVC Decoder for Energy-Efficient Software Implementation on Embedded Processors”
    Erwan Nogues, Romain Berrada, Maxime Pelcat, Daniel Menard, Erwan Raffin
    IEEE International Conference on Multimedia and Expo (ICME), Torino, Italy, 2015
    Link to the paper
  • “Energy efficiency of a parallel HEVC software decoder for embedded devices”
    Erwan Raffin, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat, Daniel Menard, Seppo Tomperi
    Proceedings of the 12th ACM International Conference on Computing Frontiers (CF’15), Ischia, Italy, 2015
    Link to the paper
  • “A modified HEVC decoder for low power decoding”
    Erwan Nogues, Erwan Raffin, Maxime Pelcat, and Daniel Menard
    Proceedings of the 12th ACM International Conference on Computing Frontiers (CF’15), Ischia, Italy, 2015
    Link to the paper
  • “Implementation of Stereo Matching Using A High Level Compiler for Parallel Computing Acceleration”
    Jinglin Zhang, Jean-François Nezan, Jean-Gabriel Cousin, Erwan Raffin
    27th Image and Vision Computing New Zealand (IVCNZ), Dunedin, New Zealand, November 26-28, 2012
    Link to the paper
  • “Exploiting reconfigurable SWP operators for multimedia applications”
    Daniel Menard, Hai-Nam Nguyen, François Charot, Stéphane Guyetant, Jérémie Guillot, Erwan Raffin, Emmanuel Casseau
    36th International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 22-27, 2011
    Link to the paper
  • “Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture”
    Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stephane Guyetant, Stephane Chevobbe and Emmanuel Casseau
    Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), Edinburgh, Scotland.
    Best Paper Award – Web links: ROMA article, DASIP article, CAIRN article
    Please read IEEE copyright notice below before downloading the full paper
  • “Architecture-Driven Synthesis of Reconfigurable Cells”
    Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, François Charot
    12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009), p531-538, Patras, Greece.
  • “How constrains programming can help you in the generation of optimized application specific reconfigurable processor extensions”
    Christophe Wolinski, Krzysztof Kuchcinski, Kevin Martin, Erwan Raffin, François Charot
    International Conference on Engineering of Reconfigurable Systems & Algorithms (ERSA’09), Las Vegas, USA (invited paper).

Workshops and Demos

  • Real-Time Low Power Software HEVC Decoder on Embedded GPP: A Side-by-Side Comparison
    E. Raffin, E. Nogues, M. Lacour, M. Pelcat, D. Menard, K. Desnos, J.F. Nezan
    Demo at Conference on Design & Architectures for Signal & Image Processing (DASIP), Cracow, Poland, 2015
    Link to the paper
  • “Low Power Software HEVC Decoder Demo for Mobile Devices”
    E. Nogues, M. Lacour, E. Raffin, M. Pelcat and D. Menard
    Demo at IEEE International Conference on Multimedia and Expo (ICME Demo 2015)
    Best Demo Award.
  • “Orcc’s Compa-Backend demonstration”
    Yaset Oliva, Emmanuel Casseau, Kevin Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickael Raulet, Erwan Raffin, Laurent Morin
    Conference on Design and Architectures for Signal and Image Processing (DASIP), Demo Night, Madrid, Spain, Oct 2014
    Link to the posterLink to the paper
  • ALCHEMY Workshop
    Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems
    Held in conjunction with the International Conference on Computational Science (ICCS 2014)
    Program Committee member (2013/2014)
    Link
  • “Graph Constraints in Embedded System Design”
    Christophe Wolinski, Krzysztof Kuchcinski, Kevin Martin, Antoine Floch, Erwan Raffin, François Charot
    Workshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Bologna, Italy
    Link to the paper
  • “Design of Processor Accelerators with Constraints”
    Christophe Wolinski, Krzysztof Kuchcinski, Kevin Martin, Erwan Raffin, François Charot
    8th workshop of the Network for Sweden-based researchers and practitioners of Constraint programming (SweConsNet 2009), Linköping, Sweden (invited talk).

 


 

Disclaimer

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All person copying this information are expected to adhere to the terms and constraints invoked by each author’s copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

IEEE Copyright Notice
Copyright 2010 IEEE. Published in the 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), scheduled for October 26-28 in Edinburgh, United Kingdom. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE. Contact: Manager, Copyrights and Permissions / IEEE Service Center / 445 Hoes Lane / P.O. Box 1331 / Piscataway, NJ 08855-1331, USA. Telephone: + Intl. 908-562-3966.